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SAW sensor reader unit using the Zynq SoC:

Principle:

The FPGA is cyclycally opening a switch which feeds the antenna for 128ns. We start sampling the I and Q lines of the hardware I/Q demodulator for 1024 samples (310MHz). Our acquisitions typically last for a few microseconds.

The user can retrieve the samples and plot them from time to time - we guarantee a continuous burst.

The FPGA focus and outputs a single point of this buffer - which can be configured by the user - to plot it on a fast D/A converter. This provides a user-friendly way to monitor the application.

The I/Q samples allow to retrieve informations such as mechanical stress undergone by the sensor or its temperature: we are measuring the signal's phase and all these effects mean phase rotations. We can easily have a very accurate image of the sensor's temperature evolution using this kind of technique.

 

In this example we heated up the sensor between two acquisitions, this shows how heat affects the signal's phase and so, how we can retrieve the temperature evolution.

 

 

 

Demonstration:

In order to provide reproducible means of generating echo delays of 1 to 3 microseconds, the antenna output of the RADAR is connected to a surface acoustic wave (SAW) delay line.

 

This component converts the incoming electromagnetic pulse into an acoustic wave which is 10^5 times slower than
the electromagnetic wave. Hence, a 1.5 mm long delay line (3 mm round trip) generates a 1 us delay in a compact setup, with insertion losses of 35 dB representative of the propagation losses of a RADAR pulse in free space.


The returned signal is translated in frequency to baseband by a hardware I/Q demodulator.
 

My Zedboard, a fast dual A/D converter (LTC2158) sampling the I and the Q line of the hardware I/Q demodulator, some hardware component to generate the RADAR pulse.

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